Verigy 93k Tester Manual New! [2026]

Set up your Device Power Supplies (DPS) to match the nominal core and I/O voltages of your chip. Configure clamping limits (voltage and current safeguards) to prevent the system from destroying expensive silicon during early debugging phases. Step 3: Configure Timing and Vectors

#include "testmethod.hpp" class ContinuityTest : public testmethod::TestMethod protected: std::string mPinList; double mCurrentLevel; protected: // Bind parameters between the SmarTest GUI and the C++ code virtual void initialize() addParameter("pinList", "string", &mPinList); addParameter("currentLevel", "double", &mCurrentLevel); // Code that executes on the tester hardware during runtime virtual void run() // 1. Select the target pins PIN_FLAGS(mPinList) = ::PIN_FLAGS::FORCE_PMU; // 2. Connect the Parametric Measurement Unit (PMU) PmuConnect(mPinList); // 3. Force current and measure the resulting voltage PmuForceCurrent(mPinList, mCurrentLevel); // 4. Trigger the measurement hardware TMW_ELEMENT tmw; PmuMeasureVoltage(mPinList, &tmw); // 5. Evaluate limits and send results to the datalog EvaluateResults(mPinList, tmw); ; REGISTER_TESTMETHOD("ContinuityTest", ContinuityTest); Use code with caution. Digital Functional Execution Template

Whether you are a test engineer debugging a complex mixed-signal device or a facility manager overseeing wafer probe, the is an indispensable resource. This article provides a structured overview of the essential documentation, hardware, software, and operational procedures for this powerful platform. 1. Introduction to the V93000 Platform

Download the official manual for your specific software version. Keep a local copy on the tester PC and a second copy on your engineering workstation. Annotate it with your own DUT-specific notes—that annotated copy will be worth more than any commercial training course. verigy 93k tester manual

Avoid unnecessary switching between different instrument states (e.g., cycling relays or swapping from PMU to digital mode frequently), as relay settling times add significant milliseconds to total test time.

The software suite governing the Verigy 93k is known as (with SmarTest 7 and SmarTest 8 being the most widely used versions). The software bridges the gap between raw physical hardware and test logic. SmarTest Workspace Core Components

The Verigy 93K tester is covered by a limited warranty. For more information, refer to the warranty documentation provided with the instrument. Set up your Device Power Supplies (DPS) to

Routes execution to a shared pattern block (e.g., an initialization sequence).

The is the low-level format. The manual teaches:

Defines clock periods, edge placements, drive phases, and strobe windows for capturing data. The manual teaches: Defines clock periods

: Tracks the physical waveforms of individual device pins. It helps troubleshoot impedance mismatches, signal reflections, and unexpected voltage drops on the Load Board.

The manual includes chapters on:

Within SmarTest, users can access documentation by selecting Help > Help Contents .