Eyeq4 Datasheet

The EyeQ4 is manufactured using (Fully Depleted Silicon On Insulator) process, which is critical for achieving high performance at low power. Specification Performance 2.5 TOPS (Tera Operations Per Second) Power Consumption ~3 Watts (nominal) Process Node 28nm FD-SOI Camera Support Up to 8 cameras simultaneously Frame Rate 36 fps (at max camera load) Package 784-pin Flip-Chip FBGA (22.5 x 22.5 mm) Safety Grade ASIL-B & AEC-Q100 Grade 2 架构组成 (Processor Architecture)

The EyeQ4 is designed for a range of ADAS and autonomous driving applications, including:

of processing power, which is roughly 10x the capability of the EyeQ3. Efficiency : Consumes approximately

The is a high-performance vision processor designed for Advanced Driver Assistance Systems (ADAS) and autonomous driving, offering a massive leap in processing power over its predecessors. Key Technical Specifications Performance : 2.5 Tera Operations Per Second (TOPS).

: Capable of 2.5 Teraflops (TFLOPS) of performance. It is approximately 10 times more powerful than the EyeQ3. eyeq4 datasheet

Six Vector Microcode Processors for dedicated image processing tasks.

+-----------------------------------------------------------------------+ | MIPS CPU Cores | | (4x Cores / 4x Threads per Core / 64-bit RISC) | +-----------------------------------------------------------------------+ | VMP Cores (6x) | MPC Cores (2x) | PMA Cores (2x) | | (Vector Microcode Eng.) | (Multi-Thread Clust) | (Prog. Macro Array) | +-----------------------------------------------------------------------+ | Image Signal Processor | +-----------------------------------------------------------------------+ Processor Subsystems

From the marketing datasheet:

Mobileye EyeQ4 is an automotive-grade vision processor (SoC) designed by Mobileye and manufactured by STMicroelectronics using 28nm FD-SOI technology. It represents a massive leap in processing power for Advanced Driver Assistance Systems (ADAS) compared to its predecessors. Core Specifications Architecture The EyeQ4 is manufactured using (Fully Depleted Silicon

Detailed hardware integration data for the EyeQ4-Mid and EyeQ4-High includes: Flip-Chip FBGA with 784 pins . Dimensions: 22.5 mm x 22.5 mm x 1.7 mm.

+-----------------------------------------------------------------------+ | MIPS CPU Cluster | | (4 Cores / 16 Hardware Threads Base Control) | +-----------------------------------------------------------------------+ | Vector Microcode | Programmable Macro | Multithreaded Processing | | Processors (VMP) | Arrays (PMA) | Clusters (MPC) | | (6 x Wide SIMD) | (Dataflow Accelerators)| (Versatile OpenCL/Algo) | +-----------------------------------------------------------------------+ | High-Bandwidth Interconnect & L2 | +-----------------------------------------------------------------------+ General-Purpose Control Layer

: Manufactured using STMicroelectronics' 28nm FD-SOI (Fully Depleted Silicon On Insulator) process, which is optimized for low power consumption.

Accommodates variable road profile reconstructions, path planning over construction zones, and localized lane boundaries. Key Technical Specifications Performance : 2

: It's built on a multi-core architecture, typically including several high-performance CPU cores and a large number of specialized cores for parallel processing, such as the SHAVE (Software Hardware Advanced Vector Engines) cores.

The EyeQ4 uses a , distributing tasks across different specialized cores to maximize efficiency. 1. CPU Cores Quantity: 4 quad-threaded MIPS InterAptiv cores.

The EyeQ4 was engineered to meet the aggressive requirements of and to act as the primary processor for Level 2 and Level 2+ automated driving systems. It handles complex, computationally intense computer vision workloads, processing feeds from up to eight cameras simultaneously . Core Technical Metrics